Which of the following digital logic families has the lowest power consumption?

CMOS (Complementary Metal-Oxide Semiconductor) logic is widely known for having the lowest power consumption among standard digital logic families. This makes it the go-to choice for battery-powered devices. The reason for this efficiency lies in its complementary design, using paired P-channel and N-channel MOSFETs. In any stable logic state (either high or low), one transistor in the pair is always turned off. Because there is no continuous path from the power supply to ground, the steady-state current draw is near zero, with power primarily consumed only during the brief moment of switching. Other logic families draw significantly more power. TTL (including Schottky TTL) and ECL (Emitter-Coupled Logic) constantly draw current even when resting. NMOS lacks the complementary "always-off" transistor arrangement, making it much less efficient than CMOS.