Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?

Noise immunity in digital circuits refers to the ability of a logic gate to ignore random voltage spikes or dips without incorrectly changing its output state. CMOS logic inherently possesses excellent noise immunity. This high immunity is because the input switching threshold of a standard CMOS gate is typically designed to be right in the middle of the voltage range, or about half of the power supply voltage (Vcc/2). Because the threshold is perfectly centered, an incoming noise spike would have to be very large—nearly half the supply voltage—to falsely trigger a logic state change. In contrast, TTL logic has a lower, asymmetrical threshold that makes it much more susceptible to noise on a low-level signal.